1. Field of the Invention
The present invention relates to an offset control circuit, an optical receiver using the same and an optical communication system. More particularly, the invention relates to an offset control circuit controlling transitionally varying offset level according to an elapsed time when a wide dynamic level is required in an optical receiver for receiving a burst signal, the optical receiver and an optical communication system.
2. Description of the Related Art
In general, an optical receiver employing an optical access system, an optical LAN, an optical interconnection and so forth, is constructed with a light receiving element receiving a digital light signal and converting into a current signal and a reception circuit amplifying the current signal and converting into a digital electric signal having a given amplitude. For an input current signal of the reception circuit in the optical receiver of this kind, a given level of an offset current is generated due to influence of an extinction ratio failure, reflected return light and a dark current generated in a light receiving element of a receiver, and so forth. At the same time, among carriers generated in response to incidence of light, a carrier generated in a portion in the light receiving element where field intensity is low, spreads gradually in a long period to cause offset current varying large time constant in comparison with a clock frequency of the signal.
If the current signal having offset is amplified, a duty ratio of an output waveform is significantly fluctuates to cause difficulty in accurate discrimination of logical xe2x80x9c0xe2x80x9d level and logical xe2x80x9c1xe2x80x9d level. Among the problems of fluctuation of the duty ratio due to offset current, the various prior arts suppressing fluctuation of duty ratio due to a given level of offset current have been proposed. For example, as shown in FIG. 19, an optical receiver circuit disclosed in Japanese Unexamined Patent Publication No. Heisei 8-84160 (corresponding to U.S. Pat. No. 5,612,810) proposes cancellation of a given level of offset respectively adding peak values of a positive-phase output and a negative-phase output of a differential pre-amplifier 20 and peak values of the negative-phase output and the positive-phase output, and can restrict fluctuation of duty ratio by setting a half value of a signal pulse amplitude as a threshold value for discriminating logical xe2x80x9c0xe2x80x9d level and logical xe2x80x9c1xe2x80x9d level irrespective of signal amplitude. In FIG. 19, the reference numeral 10 denotes a light receiving element, 40 denotes an automatic discrimination level control circuit, 31 denotes a peak-hold circuit, 32 denotes a peak-hold circuit and 37, 38 denote adder circuits, respectively.
However, the shown optical receiver circuit cannot suppress offset transitionally varying according to elapsed time to significantly vary the duty ratio of the output waveform as shown in FIG. 19. Influence of transitional variation of offset according to elapsed time for fluctuation of duty ratio of the output waveform is particularly significant when a reception dynamic range having large level difference (about 30 dB in optical level) of respective burst signals and wide dynamic range is required upon receiving a burst form optical signal in optical access system, optical LAN, optical interconnection and so forth.
An example of a passive Optical Network (PON) to be employed when such wide reception dynamic range is required, is shown in FIG. 22. In FIG. 22, respective optical transmission signal from a plurality of optical subscriber line terminal units (Optical Network Unit: ONU) 1 to 3 are synthesized by a star coupler 4 and then received by an optical receiver 6 in an optical subscriber line Terminal Station Unit (Optical Line Termination:OLT) 5. As shown, in the PON system, levels of the optical signals transmitted from respective ONUs 1 to 3 in burst manner are different respectively. Thus, in the optical receiver 6, wide dynamic range is required as set forth above.
Now, consideration is given for the case where the optical receiver 6 shown in FIG. 22 receives small level burst signal B2 after reception of large level burst signal B1. By offset due to influence of the carrier having low spreading time constant generated while the large level burst signal B1 is received, this offset may reside even upon starting of reception of the small level burst signal B2 to slowly attenuate offset at low speed time constant while small level burst signal B2 is received. In this case, a ratio of variation in elapsed time of an offset level with respect to the signal amplitude becomes non-ignorably large to cause significant fluctuation of the duty ratio of the output waveform.
As a prior art for restricting transitionally varying offset according to elapsed time, there has been proposed an optical receiver disclosed in Japanese Unexamined Patent Publication No. Heisei 10-22521 (corresponding to U.S. Pat. No. 5,737,111). A construction of the optical receiver circuit and waveform at respective portion therein are illustrated in FIG. 21. In this optical receiver, by an offset detection circuit constructed with a resistor and a capacitor, a voltage value corresponding to an offset current varying transitionally according to elapse of time, is detected. In a current drawing circuit, the detected voltage value is converted into a current to withdraw from the output current of the light receiving element. Then, the output current withdrawn the current is fed to a pre-amplifier 20. By this, an offset varying transitionally according to elapse of time can be canceled to restrict variation of the duty ratio of the output waveform.
However, in general, since the waveform of the offset current according to elapsed time which varies transitionally according to elapsed time, is different per each individual light receiving element. Therefore, in the prior art disclosed in Japanese Unexamined Patent Publication No. 10-22521, the resistance value of the resistors forming offset detecting circuit has to be adjusted individually per each individual light receiving element. Thus, the resistor has to be variable of the resistance value. For this reason, a variable resistor has to be mounted out of the chip and thus is not suited for integration of the receiving circuit into one chip. Furthermore, the resistor mounted outside of the chip inherently hinder down-sizing of the optical receiver. On the other hand, since adjustment is required for each optical receiver to incur adjustment cost for every optical receiver and thus is not suited for lowering of cost. Furthermore, since the offset detecting circuit is inserted between the light receiving element and the maximum potential power source, a bias value to be applied to the light receiving element is lowered in the extent corresponding to potential drop by the offset detecting circuit.
An object of the present invention to provide an offset control circuit which can obtain an output waveform free of fluctuation of duty ratio by canceling offset transitionally varying according to elapsed time even upon reception of an optical signal in burst form significantly variable of level difference, an optical receiver employing the same and an optical communication system.
Another object of the present invention is to provide an offset control circuit which can be realized in a form suited for integration of a receiving circuit into one chip without requiring individual adjustment by an external element, an optical receiver employing the same and an optical communication system.
According to the first aspect of the present invention, an offset control circuit comprises offset canceling means for canceling an offset component included in a pair of positive-phase and negative-phase signals and varying transitionally according to elapse of time by using at least one of a peak value and a bottom value of the positive-phase and negative-phase signals.
In the preferred construction, the offset canceling means includes a peak value holding circuit and a bottom value holding circuit holding a peak value and a bottom value of the positive-phase signals and arithmetic means for performing operation by connecting outputs of the hold circuits with the negative-phase signal in feed forward connection. In such case, the arithmetic means may include an adder circuit adding the negative-phase signal and the output signals of the peak value holding circuit and the bottom value holding circuit at substantially the same ratio.
In the alternative, the offset canceling means may include a peak value holding circuit and a bottom value holding circuit holding a peak value and a bottom value of the negative-phase signal and arithmetic means for performing operation by connecting outputs of the hold circuits with the positive-phase signal in feedforward connection. The arithmetic means may include an adder circuit adding the positive-phase signal and the output signals of the peak value holding circuit and the bottom value holding circuit at substantially the same ratio.
In the further alternative, the offset canceling means may include a first peak value holding circuit holding a peak value of the positive-phase signal, a second peak value holding circuit for holding a peak value of the negative-phase signal, a first bottom value holding circuit holding a bottom value of the positive-phase signal and a second bottom value holding circuit holding a bottom value of the negative-phase signal and arithmetic means for performing operation by connecting outputs of the hold circuits with the positive-phase and negative-phase signals in feedforward connection. The arithmetic means may include a first adder circuit adding the positive-phase signal, an output signal of the second peak value holding circuit and an output signal of the second bottom value holding circuit at substantially the same ratio, and a second adder circuit adding the negative-phase signal, an output signal of the first peak value holding circuit and an output signal of the first bottom value holding circuit at substantially the same ratio.
In the still further alternative, the offset canceling means may include a first peak value holding circuit holding a peak value of the positive-phase signal and a second peak value holding circuit for holding a peak value of the negative-phase signal, and arithmetic means for performing operation by connecting outputs of the hold circuits with the positive-phase and negative-phase signals in feedforward connection. The arithmetic means may includes a first adder circuit adding the positive-phase signal and an output signal of the second peak value holding circuit at a ratio of substantially 1:2, and a second adder circuit adding the negative-phase signal and an output signal of the first peak value holding circuit at a ratio of substantially 1:2, and a differential amplifier circuit taking output signals of the first and second adder circuits as inputs.
In the yet further alternative, the offset canceling means may includes a first bottom value holding circuit holding a bottom value of the positive-phase signal and a second bottom value holding circuit for holding a bottom value of the negative-phase signal, and arithmetic means for performing operation by connecting outputs of the hold circuits with the positive-phase and negative-phase signals in feedforward connection. The arithmetic means may include a first adder circuit adding the positive-phase signal and an output signal of the second bottom value holding circuit at a ratio of substantially 1:2, and a second adder circuit adding the negative-phase signal and an output signal of the first bottom value holding circuit at a ratio of substantially 1:2, and a differential amplifier circuit taking output signals of the first and second adder circuits as inputs.
In the still further alternative, the offset canceling means may include a bottom value holding circuit holding a bottom value of the positive-phase signal and arithmetic means for performing operation by connecting outputs of the hold circuit with the negative-phase signal in feedforward connection. The arithmetic means include an adder circuit adding the negative-phase signal and the output signals of the bottom value holding circuit at substantially the same ratio.
In the yet further alternative, the offset canceling means may include a peak value holding circuit holding a peak value of the negative-phase signal and arithmetic means for performing operation by connecting outputs of the hold circuit with the positive-phase signal in feedforward connection. In such case, the arithmetic means may include an adder circuit adding the positive-phase signal and the output signals of the peak value holding circuit at substantially the same ratio.
In the yet further embodiment, the offset canceling means may include a bottom value holding circuit holding a bottom value of the positive-phase signal and a peak value holding circuit holding a peak value of the negative-phase signal and arithmetic means for performing operation by connecting outputs of the hold circuit with the positive-phase and negative-phase signal in feedforward connection. The arithmetic means may include a first adder circuit adding the positive-phase signal and the output signals of the peak value holding circuit at substantially the same ratio and a second adder circuit adding the negative-phase signal and the output signals of the bottom value holding circuit at substantially the same ratio.
In the still further alternative, the offset canceling means may include a peak value holding circuit holding a peak value of the negative-phase signal and arithmetic means for performing operation by connecting the output signal of the hold circuit with the positive-phase signal in feedforward connection. The arithmetic means may include an adder circuit adding the positive-phase signal and an output signal of the peak value holding circuit at a ratio of substantially 1:2, and a differential amplifier circuit taking the output signal of the adder circuit and the negative-phase signal as inputs.
In the yet further alternative, the offset canceling means may includes a bottom value holding circuit holding a bottom value of the positive-phase signal and arithmetic means for performing operation by connecting outputs of the hold circuit with the negative-phase signal in feedforward connection. The arithmetic means may includes an adder circuit adding the negative-phase signal and an output signal of the peak value holding circuit at a ratio of substantially 1:2, and a differential amplifier circuit taking the output signal of the adder circuit and the positive-phase signal as inputs.
The offset control circuit may further comprise means for resetting held values of the peak value holding circuit and/or the bottom value holding circuit by inputting an external control signal.
According to the second aspect of the present invention, an optical receiver includes an offset control circuit having a construction as set forth above, a light receiving element receiving an optical input signal and a pre-amplifier amplifying an output of the light receiving element, wherein a pair of outputs of the pre-amplifier is taken as the positive-phase signal and the negative-phase signal of the offset control circuit.
The optical receiver may further comprise a discrimination level control circuit for automatically setting a threshold value for discrimination of the output signal of the offset control circuit.
According to the third aspect of the present invention, an optical communication system may employ an optical receiver as set forth above. The optical communication system may comprise a plurality of optical subscriber line terminal units transmitting a burst form optical signals at mutually different levels and an optical subscriber line terminal office unit receiving the burst form optical signals, wherein the optical subscriber line terminal office unit has the optical receiver. The held value of the peak value holding circuit and/or the bottom value holding circuit are reset within a guard time presenting between the burst form optical signal.
Operations of the present invention will be discussed. the offset component including a pair of positive-phase and the negative-phase signals and which varies transitional fashion, may be canceled using the offset component included in at least one of the peak value or the bottom value, and varying transitionally according to elapsed time. Upon cancellation, the positive-phase signal and the negative-phase signal are and at least one of the peak value and the bottom value are connected in feedforward manner to cancel the transitionally varying offset mutually.